Conventional technologies to further reduce the source inductance and resistance for semiconductor power devices including the source inductance in FET, MOSFET and JFET devices are challenged by several technical difficulties and limitations. There are ever increasing demands to reduce the source inductance and resistance in semiconductor power devices because more and more power devices are required to being used in applications that demand high efficiency, high gain, and high frequency semiconductor power devices. Reductions in source inductance can be achieved by eliminating the bond-wires in the package of a semiconductor power device. Many attempts have been made to eliminate bond-wires by configuring the semiconductor substrate as a source connection for the semiconductor power devices. There are difficulties in such approaches due to the fact that typical vertical semiconductor power devices are arranged to place the drain electrode on the substrate. The top source electrode usually requires bond wires for electrical connections during a device packaging process thus increasing the source inductance.
While silicon process technology has advanced significantly in the past decade, for the most part, the same decades-old packaging technology continues to be used as the primary packaging means. Epoxy or solder die attachment along with aluminum or gold wire bonding to a lead frame is still the dominant semiconductor packaging methodology. Advances in semiconductor processing technology, however, have made parasitics (e.g., resistances, capacitances and inductances) associated with conventional packaging techniques more of a performance-limiting factor. In the case of conventional flip chip technology, among other shortcomings, electrical connection to the back side of the die (for vertical semiconductors) is not easily facilitated. These limitations become quite significant in high current applications such as power switching devices.
U.S. Pat. No. 6,767,820 and US publication number 20010048116 disclose a chip scale package of a semiconductor MOS-gated device. A source side of a MOS-gated device wafer is covered with a passivation layer, preferably a photosensitive liquid epoxy, or a silicon nitride layer, or the like. The material is then dried and the coated wafer is exposed using standard photolithographic techniques to image the wafer and openings are formed in the passivation layer to produce a plurality of spaced exposed surface areas of the underlying source metal and a similar opening to expose the underlying gate electrode of each die on the wafer. The openings in the passivation layer are typically made through to a conventional underlying solderable top metal such as titanium, tungsten, nickel, or silver. After the openings are formed, the wafer is then sawn or otherwise singulated into individual die. The solderable drain side of the die is then connected to a U-shaped or cup-shaped drain clip, using a conductive epoxy, solder, or the like to bond the bottom drain electrode of the die to the drain clip. The bottoms of the legs of the drain clip are coplanar with the source-side surface (that is the tops of the contact projections) of the die. The U-shaped clip is usually made of a copper alloy with at least partially plated silver surfaces and is actually very thin. However, connecting dies to individual clips tends to be time consuming compared with wafer level processing. In addition, different U-shaped clips are typically needed for different die sizes, and the clips take extra space on the PC board.
US publication number 2003/0052405 discloses a vertical power MOSFET device with the drain electrode formed on the bottom surface of the silicon substrate connected to the lead frame above it whereas the gate electrode and the source electrode exposed to the bottom of the device. The MOSFET device is sealed by a resin, such as epoxy or silicone, such that the MOSFET device and an inner part of the lead frame are covered. On the bottom surface of the MOSFET device, the surface of the resin is approximately flush with surfaces of the lead frame and gate/source electrodes. That is, on the bottom surface of the semiconductor device, the bottom surface of outer lead portions of the lead frame and bottom surfaces of gate/source electrodes are exposed for connection to a conductor land (mount surface) of the mounting substrate. Then the perimeter of these gate/source electrodes is covered by the resin.
U.S. Pat. No. 6,133,634 discloses a flip chip package having a power MOSFET device including a drain terminal, a source terminal and a gate terminal. The drain terminal connects to a conductive carrier and an outer array of solder balls. The source terminal and gate terminal connect to an inner array of solder balls. The conductive carrier and the outer array of solder balls provide electrical connection between the printed circuit board and the drain terminal.
U.S. Pat. No. 6,469,384 discloses a method of packaging semiconductor devices, such as MOSFET device, which does not require a molded body. The MOSFET device is coupled to a substrate such that the source and gate regions of the die are coupled to the substrate. The MOSFET device is placed on a printed circuit board (PCB) and the surface of the die is coupled directly to the PCB with solder paste or suitable electrically conductive interconnect, and thus serves as the drain connection. The surface of the die coupled to the substrate comprises the gate region and the source region of the die. Thus, the solder ball in the gate region of the substrate serves to couple the gate region of the die to the PCB while the remaining solder balls couple the source region of the die through the substrate to the PCB.
U.S. Pat. No. 6,646,329 discloses a semiconductor device that includes a lead frame including a source pad, at least two source lead rails at a periphery of the source pad, a gate pad adjacent to the source pad, and a gate lead rail at a periphery of the gate pad. A die is coupled to the source pad and the gate pads such that a surface of the die opposite the pads is substantially flush or co-planar with the ends of the lead rails. A stiffener is coupled to the lead frame and electrically isolated therefrom.
All of the aforementioned prior art devices require modification of external packaging to allow connection to the back of the vertical semiconductor die. In general the packaging connects to the back side of the die, and wraps around the sides to become co-planar with the front of the die. However, this configuration inherently results in a footprint larger than that of the die itself, and thus is not a true CSP. In addition, the extra material required for the packaging adds to the cost of the device.
U.S. Pat. No. 6,653,740 discloses a semiconductor die package comprising a “flip-chip” that is mountable on a circuit board or other electronic interface using one surface of the chip. In particular, the package has contacts, for example, gate, source and drain electrode contacts (for a MOSFET) on the same side of the package, and can be mounted by forming solder ball contacts on the surface of the chip which interface with the external gate, source and drain pads respectively on the circuit board. External circuit components may be electrically connected to the chip using solder balls on the source electrode of the chip, the solder balls being positioned so that they will interface with appropriate source electrical connections on the circuit board. The package is configured so that the drain electrode is on the same surface at a region separate from the source electrode. A highly doped diffusion region or “sinker” extends from and beneath the top drain electrode, through the layer of relatively low carrier concentration to the substrate. The diffusion region has the same carrier concentration and type as the substrate. Thus, an electrical path is established from the source electrode, through the active elements, and into the substrate, through the diffusion region and to the top drain electrode. The drain electrode is on the same surface as the source and gate electrodes and can thus be mounted to the circuit board using solder balls that correspond to locations of appropriate external drain connections.
The preceding prior art package designs for vertical power MOSFET devices can provide electrical contacts for source, gate and drain of power devices to chip front side for individual MOSFETs. However, some techniques require extra substrates or package material to bring the backside connection to the front surface or the use of different size of solder balls. In addition, some techniques require extra processing steps to form “sinker diffusion” or contact trenches through the drift drain. In addition, using a vertical DMOS structure with drain sinkers requires large spacing between the sinker diffusions and the active regions for high voltage structures (i.e., depletion layers from body regions in the N-drift region). Furthermore, in these “sinker diffusion” techniques, the contacts are not distributed throughout the die resulting in higher overall resistance (from spreading resistance) that lowers the efficiency.
It would be desirable to produce a package design and process for its manufacture which permits wafer level processing with lower costs and a reduced footprint for individual part, and allows distributed contact throughout the die.
It is within this context that embodiments of the present invention arise.